3d 6 701 doc # 140 15 data delay devices, inc. 1 6/9 /20 14 3 mt. prospect ave. clifton, nj 07013 monolithic clock synchronizer (series 3d6 701) features ? synchronizes free - running clock to external gate signal ? input frequency range: 30mhz through 100mhz ? phase resolution: 200ps typical ? output frequency: programmable from f in to f in /256 ? output period jitter: equal to jitter of clock source ? all - silicon, low - power cmos technology ? ttl/cmos compatible inputs and outputs ? vapor phase, ir and wave solderable ? auto - insertable (dip pkg.) functional description one major drawback to using a crystal oscillator for frequency generation is that the phase of the generated clock signal cannot be synchronized to an external timing event. a delay - line oscillator (eg, the 3d7701), while supporting this feature, cannot provide the stability and jitter performance of a crystal. the 3d6 701 clock synchronizer provides the best of both worlds. the device accepts two inputs C a stable frequency source and a gate signal C and matches the phase of the clock to the gate . it also provides 8 bits of frequency scaling at the device output. the 3D6701 can be operated at 5v or 3.3v, and is offered in bot h a 16 - pin dip and a space - saving 16 - pin soic package. figure 1: timing diagram ? pin descriptions f in clock input g in gate input d0 - d7 divisor inputs sel vdd select input f out sync oscillator out vdd +3.3 or +5 volts gnd ground for mechanical dimensions, click here . for package marking details, click here . p inout 16 15 14 13 1 2 11 10 9 1 2 3 4 5 6 7 8 vdd f out d0 d2 d4 d6 g in gnd vdd sel d1 d3 d5 d7 f in gnd 3d 6701 dip - 14 3D6701d soic - 14 gin d inh fin (async) out (d=0) t res out (d=1) out (d=2)
3d6 701 doc # 140 15 dat a delay devices, inc. 2 6/9 /20 14 tel: 973 - 773 - 2299 fax: 973 - 773 - 9672 http://www.datadelay.com theory of operation the 3d6 701 clock synchronizer a rchitecture is sh own in figure 2 . the f in input is assumed to come from a stable clock source, such as a crystal oscillator. a rising edge on the g in input initiates the phase detection process. once the phase of the clock with respect to the gate has been resolved , a dela y line is adjusted to match the phase s of the two signals. there is a finite resolution to the phase detection process (typically under 500ps), so that, from one gate trigger to the next, there will remain some residual gate - to - output jitter. however, for a given gate, the jitter from one clock cycle to the next is equal to the jitter of the reference clock itself. the 3D6701 also contains a programmable divider that reduces the output frequency by an amount given by the d7:0 inputs. f out is given by f in / (d+1), so that the output frequency may range from f in (d=0) to f in / 256 (d=255). when g in returns low, the output returns to a low level and remains there until the next rising edge of g in . the performance of cmos integrated circuits is strongly depen dent on power supply stability . it is essential that the power supply pins be adequately bypassed and filtered. in addition, the power bus should be of as low an impedance construction as possible. power planes are preferred. when operating at 3.3v, tie t he sel input to gnd. when operating at 5.0v, tie the sel input to vdd. device specifications table 1: absolute maximum ratings parameter symbol min max units notes dc supply voltage v dd - 0.3 7.0 v input pin voltage v in - 0.3 v dd +0.3 v input pin current i in - 1.0 1.0 ma 25c storage temperature t strg - 55 150 c lead temperature t lead 300 c 10 sec phase resolver programmable delay line 8 - bit divider f out g in f in d7:0 figure 2: 3D6701 functional block diagram
3d 6 701 doc # 140 15 data delay devices, inc. 3 6/9 /20 14 3 mt. prospect ave. clifton, nj 07013 device specifications (contd) table 2: dc electrical characteristics ( - 40c to 85c, 3.0v to 5.25v) parameter symbol min typ max units notes static supply current* i dd 20.0 ma high level input voltage v ih 2.0 v low level input voltage v il 0.8 v high level input current i ih 1.0 ? a v ih = v dd low level input current i il 1.0 ? a v il = 0v high level output current i oh - 35.0 - 4.0 ma v dd =4.75v, v oh =2.4v low level output current i ol 4.0 15.0 ma v dd =4.75v, v ol =0.4v *i dd will vary slightly for different input clock frequencies table 3 : ac electrical characteristics ( - 40c to 85c, 3.0v to 3.6v) parameter symbol m in typ max units notes input frequency f in 30 80 mhz duty cycle dc(f in ) 40 60 % gate frequency g in 1 mhz gate inactive (low) g in,low 200 ns gate - to - out delay d inh 157 ns f in =50mhz 136 ns f in =62mhz 120 ns f in =80mhz gate - to - out de lay jitter d inh 420 ps f in =50mhz 460 ps f in =62mhz 780 ps f in =80mhz f out period jitter 50 ps reset time t res 10 ns table 4: ac electrical characteristics ( - 40c to 85c, 4.75v to 5.25v) parameter symbol min typ max units notes inpu t frequency f in 50 100 mhz duty cycle dc(f in ) 40 60 % gate frequency g in 2 mhz gate inactive (low) g in,low 125 ns gate - to - out delay d inh 138 ns f in =50mhz 118 ns f in =62mhz 106 ns f in =80mhz gate - to - out delay jitter d inh 640 ps f in =50mhz 700 ps f in =62mhz 520 ps f in =80mhz f out period jitter 50 ps reset time t res 10 ns
3d6 701 doc # 140 15 dat a delay devices, inc. 4 6/9 /20 14 tel: 973 - 773 - 2299 fax: 973 - 773 - 9672 http://www.datadelay.com silicon delay line a utomated testing test conditions input: output: ambient temperature: 25 o c ? 3 o c r load : 10k ? ? 10% supply voltage (vcc): 5 .0v ? 0.1v c load : 5pf ? 10% input pulse: high = 3.0v ? 0.1v threshold: 1.5v (rising & falling) low = 0.0v ? 0.1v source impedance: 50 ? max. rise/fall time: 3.0 ns max. (measured between 0.6 and 2.4v ) note: the above con ditions are for test only and do not in any way restrict the operation of the device. 10k ? 470 ? 5pf device under test digital scope f out out trig in ref trig figure 3: test setup device under test (dut) frequency/ time interval counter pulse generator computer system printer g in f in freq source figure 4: timing diagram 1/f osc g in f out 2.4v 1.5v 0.6v 2.4v 1.5v 0.6v t f all t r ise v ih v il 1.5v 1.5v 1.5v d inh t res
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